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CD40192BMS CD40193BMS
December 1992
CMOS Presettable Up/Down Counters (Dual Clock With Reset)
Description
CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low one-half clock cycle after the counter reaches its minimum count in the countdown mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package. The CD40192BMS and CD40193BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack
* CD40192B Only
Features
* CD40192BMS - BCD Type * CD40193BMS - Binary Type * High Voltage Type (20V Rating) * Individual Clock Lines for Counting Up or Counting Down * Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading * Asynchronous Reset and Preset Capability * Medium Speed Operation - fCL = 8MHz (typ.) at 10V * 5V, 10V and 15V Parametric Ratings * Standardize Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Up/Down Difference Counting * Multistage Ripple Counting * Synchronous Frequency Dividers * A/D and D/A Conversion * Programmable Binary or BCD Counting
*H4W, H1F *H6P,
H4X H6W
CD40193B Only
Pinout
CD40192BMS, CD40193BMS TOP VIEW
J2 Q2 Q1 1 2 3 16 VDD 15 J1 14 RESET 13 BORROW 12 CARRY 11 PRESET ENABLE 10 J3 9 J4
Functional Diagram
PRESET ENABLE J1 J2 J3 J4 CLOCK UP CLOCK DOWN 15 1 10 9 5 4 11 3 2 6 7 13 12 CARRY 14 RESET VDD = 16 VSS = 8 Q1 Q2 Q3 Q4 BORROW
CLOCK DOWN 4 CLOCK UP Q3 Q4 VSS 5 6 7 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3363
7-1419
Specifications CD40192BMS, CD40193BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20V 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20V 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 1.5 4 V V V V -55oC -55oC MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1420
Specifications CD40192BMS, CD40193BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TPHL6 TPLH6 TTHL TTLH FCL VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN o
PARAMETER Propagation Delay Clock Up or Clock Down to Q Propagation Delay Reset to Q Propagation Delay PE to Q Propagation Delay Clock Up to Carry, Clock Down to Borrow Propagation Delay PE to Borrow or Carry Propagation Delay Reset to Borrow or Carry Transition Time
SYMBOL TPHL1 TPLH1 TPHL2
CONDITIONS (NOTES 1, 2) VDD = 5V, VIN = VDD or GND
MAX 500 675 500 675 400 540 320 432 600 810 600 810 200 270 -
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
+25oC +125oC, -55oC
+25oC +125 C, -55 C +25oC +125oC, -55oC
o
2 1.48
+25oC +125oC, -55oC
+25 C +125oC, -55oC
o
+25oC +125oC, -55oC
Maximum Clock Input Frequency NOTES:
+25oC +125oC, -55oC
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 MAX 5 150 10 300 10 600 50 50 UNITS A A A A A A mV mV V V mA mA mA mA mA mA
+125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC
+125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC
7-1421
Specifications CD40192BMS, CD40193BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH5A CONDITIONS VDD = 5V, VOUT = 4.6V NOTES 1, 2 TEMPERATURE +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55oC Input Voltage Low Input Voltage High Propagation Delay Clock Up or Down to Q Propagation Delay Reset to Q Propagation Delay PE to Q Propagation Delay Clock Up to Carry, Clock Down to Borrow Propagation Delay PE to Borrow or Carry Propagation Delay Reset to Borrow or Carry Transition Time VIL VIH TPHL1 TPLH1 TPHL2 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TPHL3 TPLH3 TPHL4 TPLH4 TPHL5 TPLH5 TPHL6 TPLH6 TTHL1 TTLH1 TRCL TFCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Removal Time Reset or PE TREM VDD = 5V VDD = 10V VDD = 15V Minimum Pulse Width Reset TW VDD = 5V VDD = 10V VDD = 15V Minimum Pulse Width PE TW VDD = 5V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN 7 MAX -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 240 180 240 180 200 140 160 120 300 220 300 220 100 80 15 15 5 80 40 30 480 300 260 240 170 140 UNITS mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns ns ns ns ns ns ns ns
Maximum Clock Rise and Fall Time
7-1422
Specifications CD40192BMS, CD40193BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width SYMBOL TW CONDITIONS VDD = 5V VDD = 10V VDD = 15V Input Capacitance Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 5. The time required for RESET or PRESET ENABLE control to be removed before clocking. See timing diagram defining TREM. CIN CIN Reset All Other Inputs NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC MIN MAX 180 90 60 15 7.5 UNITS ns ns ns pF pF
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
7-1423
Specifications CD40192BMS, CD40193BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
PART NUMBER CD40192BMS, CD40193BMS Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic BurnIn (Note 1) Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 2, 3, 6, 7, 12, 13 2, 3, 6, 7, 12, 13 2, 3, 6, 7, 12, 13 1, 4, 5, 8 - 11, 14, 15 8 8, 14 8 16 1, 4, 5, 9 - 11, 14 - 16 1, 5, 9 - 11, 15, 16 1, 4, 5, 9 - 11, 14 - 16 2, 3, 6, 7, 12, 13 4 -
7-1424
CD40192BMS, CD40193BMS Logic Diagrams
*RESET
14
*PE
11 S1 R1 S2 R2 10 S3 R3 9 S4 R4
*J1
15
**
1 CONTROL LOGIC 1
**
**
*J2
*J3
*J4
**SAME AS CONTROL LOGIC 1
CARRY 12
*CLOCK UP
5
S1 S CL
S2 S CL Q1 Q2 R R2
S3 S CL Q3 R R3
S4 S CL Q4 R R4
Q1
Q2
Q3
Q4
4
R R1
*CLOCK DOWN
13 BORROW
VDD
3 Q1
2 Q2
6 Q3
7 Q4
*ALL INPUTS PROTECTED BY
VSS COS/MOS PROTECTION NETWORK
FIGURE 1. CD40192BMS LOGIC DIAGRAM (BCD)
7-1425
CD40192BMS, CD40193BMS Logic Diagrams (Continued)
*RESET
14
*PE
11 S1 R1 S2 R2 10 S3 R3 9 S4 R4
*J1
15
**
1 CONTROL LOGIC 1
**
**
*J2
*J3
*J4
**SAME AS CONTROL LOGIC 1
VSS CARRY
VDD
12
*CLOCK UP
5
S1 S CL
S2 S CL Q1 Q2 R R2
S3 S CL Q3 R R3
S4 S CL Q4 R R4
Q1
Q2
Q3
Q4
4
R R1
*CLOCK DOWN
13 VDD VDD BORROW
VDD
3 Q1
2 Q2
6 Q3
7 Q4
*ALL INPUTS PROTECTED BY
VSS COS/MOS PROTECTION NETWORK
FIGURE 2. CD40193BMS LOGIC DIAGRAM (BINARY)
7-1426
CD40192BMS, CD40193BMS
CL CL CL R S CL Q R CL p Q S p R n CL CL p n CL p n CL Q CL CL
S
=
n
CL
Q
FIGURE 3. INTERNAL LOGIC OF FLIP-FLOP TRUTH TABLE CLOCK UP CLOCK DOWN 1 1 1 1 X X 1 = High Level X X PRESET ENABLE 1 1 1 1 0 X 0 = Low Level RESET 0 0 0 0 0 1 ACTION Count Up No Count Count Down No Count Preset Reset X = Don't Care
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
FIGURE 5. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
7-1427
CD40192BMS, CD40193BMS
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 10V
GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
-10V
-10
-15V 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 400 AMBIENT TEMPERATURE (TA) = +25oC 350 300 SUPPLY VOLTAGE (VDD) = 5V 250 200 150 100 50 15V
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
10V
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
0
10
30 50 70 20 40 60 80 LOAD CAPACITANCE (CL) (pF)
90
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
106 POWER DISSIPATION PER GATE (PD) (W)
8 6 4 2
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC CL = 50pF CL = 15pF
105
8 6 4 2
104 8
6 4 2
103
8 6 4 2
102
2 4 68 2 468 2 4 68 2 4 68 2 4 68
1
10
103 104 102 INPUT FREQUENCY (fIN) (kHz)
105
FIGURE 10. DYNAMIC POWER DISSIPATION
7-1428
CD40192BMS, CD40193BMS
RESET PE J1 J2 J3 J4 CLK UP CLK DN Q1 Q2 Q3 Q4 CARRY
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
RESET PE J1 J2 J3 J4 CLK UP CLK DN Q1 Q2 Q3 Q4 CARRY
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 BORROW 0 COUNT
0
7
8901
2
1098
7
1 BORROW 0 COUNT
0
13 14 15 0 1
2
1 0 15 14 13
FIGURE 11. CD40192BMS TIMING DIAGRAM
FIGURE 12. CD40193BMS TIMING DIAGRAM
tWH CLOCK RESET PRESET ENABLE
tWL
trem*
*RESET OR PRESET ENABLE
REMOVAL TIME
FIGURE 13. TIMING DIAGRAM DEFINING trem
J1 J2 J3 J4 CLOCK UP CARRY CD40192BMS OR CD40193BMS Q1 Q2 Q3 Q4 RESET PRESET ENABLE CLOCK UP
J1 J2 J3 J4 CD40192BMS OR CD40193BMS Q1 Q2 Q3 Q4 CARRY
CLOCK DOWN
BORROW
CLOCK DOWN
BORROW
FIGURE 14. CASCADED COUNTER PACKAGES
7-1429
CD40192BMS, CD40193BMS Chip Dimensions and Pad Layout
Dimensions and pad layout for the CD40192BMSH (dimensions and pad layout for the CD40193BMSH are identical). Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
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1430

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